October 11th, 2004


FPU offload geekery

Looks like the wheel of reincarnation may be turning again, moving more floating-point power off-CPU. Clearspeed have an existing core with 64 simple FP pipelines and have announced a new core with twice the performance. A daughtercard with two cores would have a theoretical peak of 100 GFLOPS in less than 20W (they also claim 50 GFLOPS sustained real-world performance for BLAS DGEMM).

They're being pushed toward the scientific computing area, which is the obvious first place that'd want lots of cheap GFLOPS. However, I could just about see the entertainment industry wanting something like that to offload physics engines for flying and driving games, or maybe image recognition for robots or EyeToy-like interfaces, a Minority Report style hand-gesture based UI?